A task difficult to plan during an implementation phase of an application specific integrated circuit (ASIC) or a Platform ASIC design task is an engineering change order (ECO) phase. The ECOs are the steps during which a design netlist is changed, new or existing cells are moved in a layout and routing is improved to fix remaining timing and signal integrity violations (i.e., hold time or crosstalk violations). The ECO phase starts after cell placement and a first run for detailed routing of the design.
In complex multi-million gate designs, a large number of ECOs can be created and each ECO can have a turn around time of up to one week. Therefore, a duration for the ECO phase of the design is difficult to predict and thus easily causes schedule slips if underestimated. Such schedule hits are not acceptable in a rapid development environment. The high number of ECOs is caused by a high complexity of the designs and the fact that while fixing one type of violation, another type of violation is not property taken into account. As a result, the fixes for different types of violations can influence each other. Thus, a high probability exists that a change initiated by an ECO is not good enough to fix certain violations or can even create new violations.
Referring to FIG. 1, an example block diagram of a circuit 10 illustrating a logic cone containing a common hold time violation is shown. The hold time violation at a “D” input of a flip-flop 12 is caused by a first starting point at a flip-flop 14. Hold time refers to an amount of time a signal is specified to remain valid after a clock edge used to sample the signal. When a clock signal (i.e., CP) transitions, a signal at the D input to flip-flop 12 changes too rapidly due to a changing output signal at a “Q” output of the flip-flop 14.
Some conventional tools try to fix the hold time violation at an endpoint of a logic cone 16, in particular, at the D input of the flip-flop 12. For example, some conventional tools fix the hold time violation by adding a delay cell (not shown) in a net (i.e., NETA). However, adding the delay cell in the NETA creates a setup time violation from a second starting point into the logic cone 16 at a flip-flop 18. Setup time refers to an amount of time a signal is specified to remain valid before a clock edge used to sample the signal. Other conventional tools calculate that the hold time violation at the D input of the flip-flop 12 can be fixed only from the starting point of the flip-flop 14 by introducing a new setup violation for the other starting point of the logic cone 16 at the flip-flop 18. As a result, the original hold time violation is not actually fixed at all. Adding a delay cell at another point in the logic cone 16 (i.e., NETB) would solve the problem.
A number of different tools are currently available to fix different types of timing and signal integrity violations. However, the tools either work independently or at least in separate steps from each other. In practice, the results from one conventional tool (or one step of a conventional tool) are not taken into account by the other conventional tools or steps. Furthermore, manually generated netlist changes have to be run through a placement and routing tools separately. The manually generated netlist changes cannot be evaluated in context with other ECOs or be compared with other ECOs. In addition, using different conventional tools means that different setups have to be provided meaning that a lot of experience is needed by the engineers.